`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/04/18 20:59:52
// Design Name: 
// Module Name: MasterMux
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

//master-->slave mux
//slave-->master mux
module MasterMux(
AXI4_Lite.Slave m0,
AXI4_Lite.Slave m1,
AXI4_Lite.Slave m2,
AXI4_Lite.Slave m3,
AXI4_Lite.Master m,
//
input logic m0_sel_w,
input logic m1_sel_w,
input logic m2_sel_w,
input logic m3_sel_w,
output logic m_sel_w,
//
input logic m0_sel_r,
input logic m1_sel_r,
input logic m2_sel_r,
input logic m3_sel_r,
output logic m_sel_r,
//
input [2:0] cur_master_w,                 //写通道仲裁结果，据此决定哪个主机的信号给m_*,或者将m_*反馈回给哪个主机
input [2:0] cur_master_r                  //读通道仲裁结果
    );
//*************************************************************master-->slave******************************************************
always_comb
begin
   case(cur_master_w)
        3'd0:begin
	           m.awaddr=m0.awaddr;
			   m.awvalid=m0.awvalid;
			   m.wvalid=m0.wvalid;
			   m.wdata=m0.wdata;
			   m.wstrb=m0.wstrb;
			   m_sel_w=m0_sel_w;
			   m.bready=m0.bready;
			end
	    3'd1:begin
	           m.awaddr=m1.awaddr;
			   m.awvalid=m1.awvalid;
			   m.wvalid=m1.wvalid;
			   m.wdata=m1.wdata;
			   m.wstrb=m1.wstrb;
			   m_sel_w=m1_sel_w;
			   m.bready=m1.bready;
			end
		3'd2:begin
	           m.awaddr=m2.awaddr;
			   m.awvalid=m2.awvalid;
			   m.wvalid=m2.wvalid;
			   m.wdata=m2.wdata;
			   m.wstrb=m2.wstrb;
			   m_sel_w=m2_sel_w;
			   m.bready=m2.bready;
			end
		3'd3:begin
	           m.awaddr=m3.awaddr;
			   m.awvalid=m3.awvalid;
			   m.wvalid=m3.wvalid;
			   m.wdata=m3.wdata;
			   m.wstrb=m3.wstrb;
			   m_sel_w=m3_sel_w;
			   m.bready=m3.bready;
			end
	endcase
end
//************************************************************slave-->master************************************************************
//m0_awready,m1_awready,m2_awready,m3_awready
always_comb
begin
    if(cur_master_w==3'd0)
	    m0.awready=m.awready;
	else
	    m0.awready=0;
end
always_comb
begin
    if(cur_master_w==3'd1)
	    m1.awready=m.awready;
	else
	    m1.awready=0;
end
always_comb
begin
    if(cur_master_w==3'd2)
	    m2.awready=m.awready;
	else
	    m2.awready=0;
end
always_comb
begin
    if(cur_master_w==3'd3)
	    m3.awready=m.awready;
	else
	    m3.awready=0;
end
//m0_wready,m1_wready,m2_wready,m3_wready
always_comb
begin
    if(cur_master_w==3'd0)
	    m0.wready=m.wready;
	else
	    m0.wready=0;
end
always_comb
begin
    if(cur_master_w==3'd1)
	    m1.wready=m.wready;
	else
	    m1.wready=0;
end
always_comb
begin
    if(cur_master_w==3'd2)
	    m2.wready=m.wready;
	else
	    m2.wready=0;
end
always_comb
begin
    if(cur_master_w==3'd3)
	    m3.wready=m.wready;
	else
	    m3.wready=0;
end
//m0_bvalid,m1_bvalid,m2_bvalid,m3_bvalid
always_comb
begin  
    if(cur_master_w==3'd0)
	    m0.bvalid=m.bvalid;
	else
	    m0.bvalid=0;
end
always_comb
begin  
    if(cur_master_w==3'd1)
	    m1.bvalid=m.bvalid;
	else
	    m1.bvalid=0;
end
always_comb
begin  
    if(cur_master_w==3'd2)
	    m2.bvalid=m.bvalid;
	else
	    m2.bvalid=0;
end
always_comb
begin  
    if(cur_master_w==3'd3)
	    m3.bvalid=m.bvalid;
	else
	    m3.bvalid=0;
end
//m0_bresp,m1_bresp,m2_bresp,m3_bresp
always_comb
begin
   if(cur_master_w==3'd0)
      m0.bresp=m.bresp;
   else
      m0.bresp=2'b00;
end
always_comb
begin
   if(cur_master_w==3'd1)
      m1.bresp=m.bresp;
   else
      m1.bresp=2'b00;
end
always_comb
begin
   if(cur_master_w==3'd2)
      m2.bresp=m.bresp;
   else
      m2.bresp=2'b00;
end
always_comb
begin
   if(cur_master_w==3'd3)
      m3.bresp=m.bresp;
   else
      m3.bresp=2'b00;
end
//***************************************************************读********************************************************
//master-->slave
always_comb
begin
   case(cur_master_r)
      3'd0:begin
	          m.arvalid=m0.arvalid;
			  m.araddr=m0.araddr;
			  m.rready=m0.rready;
			  m_sel_r=m0_sel_r;
		   end
	  3'd1:begin
	          m.arvalid=m1.arvalid;
			  m.araddr=m1.araddr;
			  m.rready=m1.rready;
			  m_sel_r=m1_sel_r;
		   end
	  3'd2:begin
	          m.arvalid=m2.arvalid;
			  m.araddr=m2.araddr;
			  m.rready=m2.rready;
			  m_sel_r=m2_sel_r;
		   end
	  3'd3:begin
	          m.arvalid=m3.arvalid;
			  m.araddr=m3.araddr;
			  m.rready=m3.rready;
			  m_sel_r=m3_sel_r;
		   end
	  default:begin
	          m.arvalid=0;
			  m.araddr=0;
			  m.rready=0;
			  m_sel_r=0;
		   end
	endcase
end
//slave-->master
always_comb
begin
   m0.arready=0;
   m0.rdata=0;
   m0.rvalid=0;
   m0.rresp=0;
   m1.arready=0;
   m1.rdata=0;
   m1.rvalid=0;
   m1.rresp=0;
   m2.arready=0;
   m2.rdata=0;
   m2.rvalid=0;
   m2.rresp=0;
   m3.arready=0;
   m3.rdata=0;
   m3.rvalid=0;
   m3.rresp=0;
   case(cur_master_r)
      3'd0:begin
	          m0.arready=m.arready;
			  m0.rvalid=m.rvalid;
			  m0.rresp=m.rresp;
			  m0.rdata=m.rdata;
		   end
	   3'd1:begin
	          m1.arready=m.arready;
			  m1.rvalid=m.rvalid;
			  m1.rresp=m.rresp;
			  m1.rdata=m.rdata;
		   end
	   3'd2:begin
	          m2.arready=m.arready;
			  m2.rvalid=m.rvalid;
			  m2.rresp=m.rresp;
			  m2.rdata=m.rdata;
		   end
	   3'd3:begin
	          m3.arready=m.arready;
			  m3.rvalid=m.rvalid;
			  m3.rresp=m.rresp;
			  m3.rdata=m.rdata;
		   end
	  endcase
end
endmodule
